Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel Processing
نویسنده
چکیده
ABSTRACT:The main objectives of any VLSI design are to achieve the low Power, minimum Delay and Area reduction. Minimizing power, delay & area is a challenge in the present situation, but all efforts to achieve one of these can lead to a better design. This paper proposes an EDA tool for low power/ high speed VLSI design, which solves any DFG to estimate the speed of operation and the percentage reduction in the power consumption using pipelining and parallel processing concepts.
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Modified 32-Bit Shift-Add Multiplier Design for Low Power Application
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